{"title":"具有减少导通状态开关的改进结构9电平逆变器(MS9LI)","authors":"Vijayakumar Arun;Sundaramoorthy Prabhu;Natarajan Prabaharan;Balashanmugham Shanthi","doi":"10.1109/ICJECE.2022.3222215","DOIUrl":null,"url":null,"abstract":"This article describes a modified structure 9-level inverter (MS9LI) with a dual dc link and eight switches. The dual dc links are different dc voltage sources with a 1:3 ratio. To generate high-quality nine-level output, the alternative phase opposition and disposition pulsewidth modulation (APODPWM) technique has been used. Most reported reduced device multilevel inverters (MLIs) include several underutilized dc sources and much more active switches. The designed MS9LI is more efficient since it uses fewer conducting switches. The proposed configuration furthermore does not need a backend H-bridge, and voltage stress is not more than the input dc voltage. A series connection of the proposed configuration can also be used to extend the topology. To prove the superior performance of the proposed MS9LI configuration, a detailed comparison with the foremost configurations in terms of the essential number of sources, switches, and drivers is made. In order to confirm the viability and functionality of the MS9LI configuration, various simulation and experimental findings are presented.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"46 1","pages":"15-23"},"PeriodicalIF":2.1000,"publicationDate":"2023-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Modified Structure 9-Level Inverter (MS9LI) With Reduced On-State Switches\",\"authors\":\"Vijayakumar Arun;Sundaramoorthy Prabhu;Natarajan Prabaharan;Balashanmugham Shanthi\",\"doi\":\"10.1109/ICJECE.2022.3222215\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article describes a modified structure 9-level inverter (MS9LI) with a dual dc link and eight switches. The dual dc links are different dc voltage sources with a 1:3 ratio. To generate high-quality nine-level output, the alternative phase opposition and disposition pulsewidth modulation (APODPWM) technique has been used. Most reported reduced device multilevel inverters (MLIs) include several underutilized dc sources and much more active switches. The designed MS9LI is more efficient since it uses fewer conducting switches. The proposed configuration furthermore does not need a backend H-bridge, and voltage stress is not more than the input dc voltage. A series connection of the proposed configuration can also be used to extend the topology. To prove the superior performance of the proposed MS9LI configuration, a detailed comparison with the foremost configurations in terms of the essential number of sources, switches, and drivers is made. In order to confirm the viability and functionality of the MS9LI configuration, various simulation and experimental findings are presented.\",\"PeriodicalId\":100619,\"journal\":{\"name\":\"IEEE Canadian Journal of Electrical and Computer Engineering\",\"volume\":\"46 1\",\"pages\":\"15-23\"},\"PeriodicalIF\":2.1000,\"publicationDate\":\"2023-02-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Canadian Journal of Electrical and Computer Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10050856/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Canadian Journal of Electrical and Computer Engineering","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10050856/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Modified Structure 9-Level Inverter (MS9LI) With Reduced On-State Switches
This article describes a modified structure 9-level inverter (MS9LI) with a dual dc link and eight switches. The dual dc links are different dc voltage sources with a 1:3 ratio. To generate high-quality nine-level output, the alternative phase opposition and disposition pulsewidth modulation (APODPWM) technique has been used. Most reported reduced device multilevel inverters (MLIs) include several underutilized dc sources and much more active switches. The designed MS9LI is more efficient since it uses fewer conducting switches. The proposed configuration furthermore does not need a backend H-bridge, and voltage stress is not more than the input dc voltage. A series connection of the proposed configuration can also be used to extend the topology. To prove the superior performance of the proposed MS9LI configuration, a detailed comparison with the foremost configurations in terms of the essential number of sources, switches, and drivers is made. In order to confirm the viability and functionality of the MS9LI configuration, various simulation and experimental findings are presented.