小动物遥测系统的设计

IF 0.6 Q4 COMPUTER SCIENCE, INFORMATION SYSTEMS Journal of Communications Software and Systems Pub Date : 2021-01-01 DOI:10.24138/jcomss-2021-0065
Abdelali El Boutahiri, K. Khadiri, A. Tahiri, H. Qjidaa
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引用次数: 1

摘要

小型动物遥测系统的外部单元使用感应链路将数据和电力传输到小型植入物。在这项工作中,首先,我们提出了一个宽带频移键控(FSK)发射机,它是一个E类功率放大器(PA)在两个负载网络之间的开关,使PA在两个输入时钟频率下正确调谐。用于数据调制的载波频率为5MHz/10MHz,拟议链路的数据速率为2.5 Mbps。另一方面,本文对内部单元的模拟电路进行了设计。内部单元具有解调器电路,用于直接从FSK载波导出频率时钟并对二进制数据流进行采样。它也有一个低功率的发电机电路产生电源电压到其他模块。低功率发电机由高效率、低功率整流器和低功率稳压器组成。为了最小化稳压器的静态电流,我们提出了一个控制部分,它是一个两级误差放大器,用于控制稳压器差分对中使用的PMOS晶体管的栅极电压,从而稳定其输出信号(Vreg)的直流(DC)电平。该发生器电路的输出电压被调节为1V,模拟的静态电流约为9.9μA,线路调节性能仅为8mV/V。采用Cadence在180 nm CMOS工艺下对所提出的电路进行了设计和仿真。
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A Design of Telemetry System for Small Animals
The external unit of small telemetry system for animals uses inductive link to transmit both data and power to a small implant. In this work, firstly, we have presented a wideband frequency shift keying (FSK) transmitter, which is a class E power amplifier (PA) switches between two load networks that make the PA tuned correctly at tow input clock frequencies. Carrier frequencies used for data modulation are 5MHz/10MHz, the data rate of the proposed link is 2.5 Mbps. On the other hand, the analog circuits of the internal unit are designed in this paper. Internal unit has a demodulator circuit to derive directly a frequency clock from the FSK carrier and to sample the binary data stream. It also has a low power generator circuit to generate the supply voltage to the other blocks. The low power generator is composed of a high efficiency, low power rectifier, and a low power voltage regulator. To minimize the quiescent current of the regulator, we propose a control section which is a two-stage error amplifier to control the gate voltage of the PMOS transistors used in the differential pair of the voltage regulator and thus stabilize the direct current (DC) level at its output signal (Vreg). The output voltage of the proposed generator circuit is regulated at 1V, the quiescent current simulated is about 9.9μA and the line regulation performance is only 8mV/V. All circuits proposed in this paper were designed and simulated using Cadence in 180 nm CMOS technology.
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来源期刊
Journal of Communications Software and Systems
Journal of Communications Software and Systems Engineering-Electrical and Electronic Engineering
CiteScore
2.00
自引率
14.30%
发文量
28
审稿时长
8 weeks
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