界面陷阱对高迁移率信道性能的影响

2010 Silicon Nanoelectronics Workshop Pub Date : 2010-06-13 DOI:10.1109/SNW.2010.5562597

G. Hellings, G. Eneman, G. Brammertz, K. Martens, J. Mitard, Wei-E. Wang, T. Hoffmann, M. Meuris, K. De Meyer

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引用次数: 0

摘要

提出并验证了一种技术来预测由于界面陷阱及其能量分布导致的MOSFET性能的静电退化。它提供了基于提取的界面陷阱光谱的亚阈值斜率退化的估计，而无需晶体管制造。

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Influence of interface traps on high-mobility channel performance

A technique is presented and verified to predict the electrostatic degradation of MOSFET performance, due to interface traps and their energy distribution. It provides an estimate of the technology's sub-threshold slope degradation based on an extracted interface traps spectrum, without the need for transistor fabrication.

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2010 Silicon Nanoelectronics Workshop

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