哈希函数Luffa的硬件实现

Akashi Satoh, T. Katashita, T. Sugawara, N. Homma, T. Aoki
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引用次数: 1

摘要

本文介绍了哈希算法Luffa的硬件架构,Luffa是下一代哈希标准SHA-3的候选算法。该架构采用90纳米CMOS标准单元库实现。高速架构的高吞吐量为35 Gbps,紧凑架构的门数为14.7 kgate。与海绵功能类别中的其他SHA-3候选算法Keccak以及当前的哈希标准SHA-256相比,Luffa显示出从高速到紧凑电路的灵活实现优势。
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Hardware implementations of hash function Luffa
This paper presents hardware architectures for the hash algorithm Luffa, which is a candidate for the next-generation hash standard SHA-3. The architectures were implemented by using a 90-nm CMOS standard cell library. A high throughput of 35 Gbps for a high-speed architecture and a gate count of 14.7 kgate for a compact architecture were obtained. In comparison with Keccak, other SHA-3 candidate in the sponge function category, as well as with the current hash standard SHA-256, Luffa exhibited the advantage of flexible implementation ranging from high-speed to compact circuits.
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