Enhance the Lifetime of PCM Memory by Reducing the Bit Flips

Memory technology has been growing at a very fast rate in these past few years and the recent trend of replacing Volatile memories such as DRAM, with NonVolatile Memory (NVM) technologies such as Phase change Memory (PCM) and Spin Transfer Torque RAM(STT-RAM) is becoming more prevalent. But their drawback of not having a lifetime comparable to that of their Volatile counterparts, has still kept the idea of NVMs as cache, still a challenge. Apart from this, the information wm resist in the memory even though power is off and this may lead to data threats. Hence, to protect sensitive data, the Advanced Encryption Standard Counter Mode (AES-CTR) algorithm is used to encrypt the information, which is have a huge number of bit flips to be written on the memory. This paper deals with one such method to have the higher lifetime of NVM, namely PCM by having lesser the bit transitions to be written on the memory. The proposed architecture is implemented in Gem5 simulator and also synthesized and implemented using Xilinx ISE 14.7. The model has also been simulated using Parsec and iSim using standardized test vectors and the result shows that 5% improvement in lifetime is observed, 21% and 25% of the hardware components are utilized for read and write phase.