Brendan Mullane, Vincent O’Brien, Ciaran MacNamee, Thomas Fleischmann
{"title":"一个用于ADC测试和测量的SOC平台","authors":"Brendan Mullane, Vincent O’Brien, Ciaran MacNamee, Thomas Fleischmann","doi":"10.1109/DDECS.2009.5012087","DOIUrl":null,"url":null,"abstract":"An Analog to Digital Converter Built-in-Self-Test design for System-on-Chip applications is presented. Linear and dynamic ADC test occur in parallel to reduce overall test time. A ramp generator is used for linear histogram measurements and a sine-wave signal is applied for dynamic tests. The design precisely measures Hits-per-Code enabling accurate linearity test and a low-area optimal CPU operates dynamic measurements. Results demonstrate efficient silicon area overheads and lower test time capability.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"45 1","pages":"4-7"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"An SOC platform for ADC test and measurement\",\"authors\":\"Brendan Mullane, Vincent O’Brien, Ciaran MacNamee, Thomas Fleischmann\",\"doi\":\"10.1109/DDECS.2009.5012087\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An Analog to Digital Converter Built-in-Self-Test design for System-on-Chip applications is presented. Linear and dynamic ADC test occur in parallel to reduce overall test time. A ramp generator is used for linear histogram measurements and a sine-wave signal is applied for dynamic tests. The design precisely measures Hits-per-Code enabling accurate linearity test and a low-area optimal CPU operates dynamic measurements. Results demonstrate efficient silicon area overheads and lower test time capability.\",\"PeriodicalId\":6325,\"journal\":{\"name\":\"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems\",\"volume\":\"45 1\",\"pages\":\"4-7\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DDECS.2009.5012087\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2009.5012087","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Analog to Digital Converter Built-in-Self-Test design for System-on-Chip applications is presented. Linear and dynamic ADC test occur in parallel to reduce overall test time. A ramp generator is used for linear histogram measurements and a sine-wave signal is applied for dynamic tests. The design precisely measures Hits-per-Code enabling accurate linearity test and a low-area optimal CPU operates dynamic measurements. Results demonstrate efficient silicon area overheads and lower test time capability.
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