Area-Efficient Fault-Tolerant Design for Low-Density Parity-Check Decoders

As technology moves into nano-realm, large area of the chip is especially vulnerable to single event upset (SEU) in space applications. In this paper, low cost fault-tolerant schemes are presented for the key modules of Low-Density Parity-Check (LDPC) code decoder to save logic resources. For counters, a fault-tolerant scheme based on m-sequence and Hamming coding is proposed, whereby the soft errors generated by SEUs can be located and corrected by a simple Hamming decoder. For RAM contents, we first propose a layered pipelined architecture absorbing LLR RAM into V2C RAM to reduce memory bits, which will lower the impact of SEUs. Then, a RAM hardening scheme is proposed, which only requires to detect soft errors by parity check, while the error correction is accomplished by decoder's own iterative decoding capability that has not been exploited sufficiently. Simulation results show that the proposed fault-tolerant counter could totally avoid SEUs and saves 42% of cell area compared with TMR method and the layered pipelined architecture saves 42% and 12% of memory bits compared with [4] and [15]. In addition, the hardened RAM cells will not cause extra bit errors when a soft error happens under the environments of high signal-to-noise ratio (SNR). The cost is only one parity bit for each RAM content, which is much less than conventional hardening schemes.