SystemC modelling of lossless compression IP cores for space applications

In this paper, we perform the Electronic System Level (ESL) modelling and verification of two lossless compression standard algorithms for space applications using the SystemC language. In particular we present the architectures and a description in SystemC of the CCSDS-121 universal lossless compressor and the CCSDS-123 lossless compressor for hyperspectral and multispectral images. Both algorithms were specifically designed to operate on board satellites and they can be utilized as independent standalone compressors as well as jointly. In the latter case, the CCSDS-121 performs the entropy coding stage of the CCSDS-123 compressor. The computational capabilities of the hardware available on a satellite are limited, and hence, it is necessary to design hardware architectures that make it possible to execute the algorithms in an efficient way in terms of throughput, resource utilization and power consumption. On-board compression algorithms are usually implemented on ASICs or FPGAs that are tolerant to solar radiation. The main objective of this work is to describe models of the compressors in SystemC, that enable the generation of specifications for a subsequent implementation phase where the algorithms will be described in a hardware design language (VHDL) that can be efficiently mapped into space-qualified FPGAs. With the SystemC models, we perform an exploration of the design space, refining the architecture, and retrieving information about the limits in performance of the cores, storage requirements, data dependencies and prospective hardware requirements of the later FPGA implementation. The described models also comprise connections to shared communication buses using transaction-level modelling (TLM), allowing their inclusion in an embedded system model that may include a software co-processor as well as other processing cores. Additionally, the models are verified by creating SystemC testbenches that can be reused to verify the IP cores when described in VHDL.