{"title":"Kalray MPPA®:大规模并行处理器阵列:重新访问DSP加速与Kalray MPPA多核处理器","authors":"B. Dinechin","doi":"10.1109/HOTCHIPS.2015.7477332","DOIUrl":null,"url":null,"abstract":"Presents a collection of slides covering the following topics: manycore processor roadmap; field-programmable gate arrays (FPGA); digital signal processors (DSP); graphics processing units (GPU); Intel many integrated core (MIC); Bostan processor architecture; and supecomputing on a chip.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"145 1","pages":"1-27"},"PeriodicalIF":0.0000,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"24","resultStr":"{\"title\":\"Kalray MPPA®: Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor\",\"authors\":\"B. Dinechin\",\"doi\":\"10.1109/HOTCHIPS.2015.7477332\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Presents a collection of slides covering the following topics: manycore processor roadmap; field-programmable gate arrays (FPGA); digital signal processors (DSP); graphics processing units (GPU); Intel many integrated core (MIC); Bostan processor architecture; and supecomputing on a chip.\",\"PeriodicalId\":6666,\"journal\":{\"name\":\"2015 IEEE Hot Chips 27 Symposium (HCS)\",\"volume\":\"145 1\",\"pages\":\"1-27\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"24\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Hot Chips 27 Symposium (HCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HOTCHIPS.2015.7477332\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Hot Chips 27 Symposium (HCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTCHIPS.2015.7477332","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Kalray MPPA®: Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor
Presents a collection of slides covering the following topics: manycore processor roadmap; field-programmable gate arrays (FPGA); digital signal processors (DSP); graphics processing units (GPU); Intel many integrated core (MIC); Bostan processor architecture; and supecomputing on a chip.
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