Yicheng Zhu, Ting Ge, N. Ellis, Jiarui Zou, R. Pilawa-Podgurski
{"title":"一种用于超高电流应用的48v - 1v开关母线转换器","authors":"Yicheng Zhu, Ting Ge, N. Ellis, Jiarui Zou, R. Pilawa-Podgurski","doi":"10.1109/COMPEL52896.2023.10221149","DOIUrl":null,"url":null,"abstract":"This paper presents an ultra-high-current switching bus converter with direct 48-V-to-1-V power conversion for next-generation ultra-high-power digital loads (e.g., CPUs, GPUs, ASICs, etc.). In the proposed topology, two 2-to-1 switched-capacitor (SC) front-ends are merged with four 10-branch series-capacitor buck (SCB) modules through two switching buses. Compared to the DC-bus-based architecture, the switching-bus-based architecture does not require DC bus capacitors, reduces the number of switches, and ensures complete soft-charging operation. Through two-phase operation within each SCB module, the switching bus converter extends the maximum duty ratio and achieves a very large SC stage conversion ratio of 20-to-1. Compared to existing 48-V-to-1-V hybrid SC demonstrations, the proposed topology has the lowest normalized switch stress and the smallest normalized passive component volume, showing great potential for both higher efficiency and higher power density than prior solutions. A 48-V-to-1-V hardware prototype was designed and built with custom four-phase coupled inductors and gate drive daughterboards. Hybrid gate drive circuitry comprising gate-driven charge pump circuits and cascaded bootstrap circuits was customized for the high-side switches in the SCB modules to overcome the challenge of accumulative voltage drops in the conventional cascaded bootstrap circuit. The hardware prototype was tested up to 1200-A output current and achieved 92.4% peak system efficiency, 87.5% full-load efficiency (including gate drive loss), and 607 W/in3 power density (by box volume).","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"57 1","pages":"1-8"},"PeriodicalIF":1.0000,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 48-V-to-1-V Switching Bus Converter for Ultra-High-Current Applications\",\"authors\":\"Yicheng Zhu, Ting Ge, N. Ellis, Jiarui Zou, R. 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Compared to existing 48-V-to-1-V hybrid SC demonstrations, the proposed topology has the lowest normalized switch stress and the smallest normalized passive component volume, showing great potential for both higher efficiency and higher power density than prior solutions. A 48-V-to-1-V hardware prototype was designed and built with custom four-phase coupled inductors and gate drive daughterboards. Hybrid gate drive circuitry comprising gate-driven charge pump circuits and cascaded bootstrap circuits was customized for the high-side switches in the SCB modules to overcome the challenge of accumulative voltage drops in the conventional cascaded bootstrap circuit. The hardware prototype was tested up to 1200-A output current and achieved 92.4% peak system efficiency, 87.5% full-load efficiency (including gate drive loss), and 607 W/in3 power density (by box volume).\",\"PeriodicalId\":55233,\"journal\":{\"name\":\"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering\",\"volume\":\"57 1\",\"pages\":\"1-8\"},\"PeriodicalIF\":1.0000,\"publicationDate\":\"2023-06-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://doi.org/10.1109/COMPEL52896.2023.10221149\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1109/COMPEL52896.2023.10221149","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS","Score":null,"Total":0}
A 48-V-to-1-V Switching Bus Converter for Ultra-High-Current Applications
This paper presents an ultra-high-current switching bus converter with direct 48-V-to-1-V power conversion for next-generation ultra-high-power digital loads (e.g., CPUs, GPUs, ASICs, etc.). In the proposed topology, two 2-to-1 switched-capacitor (SC) front-ends are merged with four 10-branch series-capacitor buck (SCB) modules through two switching buses. Compared to the DC-bus-based architecture, the switching-bus-based architecture does not require DC bus capacitors, reduces the number of switches, and ensures complete soft-charging operation. Through two-phase operation within each SCB module, the switching bus converter extends the maximum duty ratio and achieves a very large SC stage conversion ratio of 20-to-1. Compared to existing 48-V-to-1-V hybrid SC demonstrations, the proposed topology has the lowest normalized switch stress and the smallest normalized passive component volume, showing great potential for both higher efficiency and higher power density than prior solutions. A 48-V-to-1-V hardware prototype was designed and built with custom four-phase coupled inductors and gate drive daughterboards. Hybrid gate drive circuitry comprising gate-driven charge pump circuits and cascaded bootstrap circuits was customized for the high-side switches in the SCB modules to overcome the challenge of accumulative voltage drops in the conventional cascaded bootstrap circuit. The hardware prototype was tested up to 1200-A output current and achieved 92.4% peak system efficiency, 87.5% full-load efficiency (including gate drive loss), and 607 W/in3 power density (by box volume).
期刊介绍:
COMPEL exists for the discussion and dissemination of computational and analytical methods in electrical and electronic engineering. The main emphasis of papers should be on methods and new techniques, or the application of existing techniques in a novel way. Whilst papers with immediate application to particular engineering problems are welcome, so too are papers that form a basis for further development in the area of study. A double-blind review process ensures the content''s validity and relevance.