S. Saeedi, S. Mehrmanesh, H. A. Aslanzadeh, S. M. Atarodi
{"title":"一种1.5 v 14位CMOS DAC，具有一种新的无线通信系统自校准技术","authors":"S. Saeedi, S. Mehrmanesh, H. A. Aslanzadeh, S. M. Atarodi","doi":"10.1109/ICECS.2003.1301904","DOIUrl":null,"url":null,"abstract":"A 14-bit 1.5 V CMOS current steering digital to analog converter (DAC) with a new calibration technique is presented. This technique is suitable for low voltage applications and does not require digital computation and correction circuits and additional calibration DAC. The circuit has been designed and simulated in a standard 0.18 /spl mu/m CMOS technology. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are better than 0.35 LSB and 0.15 LSB, respectively. The power consumption of analog circuits is 33 mW, whereas the digital part consumes 48 mW.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"1 1","pages":"786-789 Vol.2"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 1.5-V 14-bit CMOS DAC with a new self-calibration technique for wireless communication systems\",\"authors\":\"S. Saeedi, S. Mehrmanesh, H. A. Aslanzadeh, S. M. Atarodi\",\"doi\":\"10.1109/ICECS.2003.1301904\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 14-bit 1.5 V CMOS current steering digital to analog converter (DAC) with a new calibration technique is presented. This technique is suitable for low voltage applications and does not require digital computation and correction circuits and additional calibration DAC. The circuit has been designed and simulated in a standard 0.18 /spl mu/m CMOS technology. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are better than 0.35 LSB and 0.15 LSB, respectively. The power consumption of analog circuits is 33 mW, whereas the digital part consumes 48 mW.\",\"PeriodicalId\":36912,\"journal\":{\"name\":\"Czas Kultury\",\"volume\":\"1 1\",\"pages\":\"786-789 Vol.2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-12-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Czas Kultury\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2003.1301904\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"Arts and Humanities\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Czas Kultury","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2003.1301904","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Arts and Humanities","Score":null,"Total":0}
引用次数: 4
摘要
介绍了一种采用新型校准技术的14位1.5 V CMOS电流转向数模转换器(DAC)。该技术适用于低电压应用，不需要数字计算和校正电路以及额外的校准DAC。电路在标准的0.18 /spl mu/m CMOS工艺下进行了设计和仿真。所提出的14位规格DAC的积分和微分非线性分别优于0.35 LSB和0.15 LSB。模拟电路的功耗为33兆瓦，而数字部分的功耗为48兆瓦。
A 1.5-V 14-bit CMOS DAC with a new self-calibration technique for wireless communication systems
A 14-bit 1.5 V CMOS current steering digital to analog converter (DAC) with a new calibration technique is presented. This technique is suitable for low voltage applications and does not require digital computation and correction circuits and additional calibration DAC. The circuit has been designed and simulated in a standard 0.18 /spl mu/m CMOS technology. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are better than 0.35 LSB and 0.15 LSB, respectively. The power consumption of analog circuits is 33 mW, whereas the digital part consumes 48 mW.
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