{"title":"采用0.18μm技术实现非易失性4×4 4T1D DRAM单元","authors":"T. Joseph, Ajith Ravindran","doi":"10.1109/ICCICCT.2014.6993001","DOIUrl":null,"url":null,"abstract":"This paper deals with the design and evolution of different 4×4 bit DRAM cells. Performances of different volatile 4×4 DRAM cells are compared. The comparison is done on the basis of power, area and delay. The 4×4 Non-Volatile (NVDRAM 4T1D) cell is proposed. The performance of the NVDRAM is then examined. The schematic entry was done using Mentor Graphics Design architect and simulations are done using Mentor Graphics Eldo. The simulation results obtained with TSMC 0.18μm process technology at 1.8V.","PeriodicalId":6615,"journal":{"name":"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)","volume":"507 1","pages":"435-439"},"PeriodicalIF":0.0000,"publicationDate":"2014-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Implementation of non-volatile 4×4 4T1D DRAM cell in 0.18μm technology\",\"authors\":\"T. Joseph, Ajith Ravindran\",\"doi\":\"10.1109/ICCICCT.2014.6993001\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper deals with the design and evolution of different 4×4 bit DRAM cells. Performances of different volatile 4×4 DRAM cells are compared. The comparison is done on the basis of power, area and delay. The 4×4 Non-Volatile (NVDRAM 4T1D) cell is proposed. The performance of the NVDRAM is then examined. The schematic entry was done using Mentor Graphics Design architect and simulations are done using Mentor Graphics Eldo. The simulation results obtained with TSMC 0.18μm process technology at 1.8V.\",\"PeriodicalId\":6615,\"journal\":{\"name\":\"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)\",\"volume\":\"507 1\",\"pages\":\"435-439\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-07-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCICCT.2014.6993001\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCICCT.2014.6993001","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Implementation of non-volatile 4×4 4T1D DRAM cell in 0.18μm technology
This paper deals with the design and evolution of different 4×4 bit DRAM cells. Performances of different volatile 4×4 DRAM cells are compared. The comparison is done on the basis of power, area and delay. The 4×4 Non-Volatile (NVDRAM 4T1D) cell is proposed. The performance of the NVDRAM is then examined. The schematic entry was done using Mentor Graphics Design architect and simulations are done using Mentor Graphics Eldo. The simulation results obtained with TSMC 0.18μm process technology at 1.8V.
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