{"title":"高k栅极介电介质纳米级FinFET中ses的分析","authors":"Qian Xie, Jun Xu","doi":"10.1109/SNW.2010.5562569","DOIUrl":null,"url":null,"abstract":"We derive a three-dimensional (3-D) analytical model of scale length for nanoscale SOI tri-gate FET (SOI-FinFET) and discuss its significance. This work takes into account the difference in permittivity between the fin (channel) and the gate insulator, and thus permits this model accurate for the analysis of SCEs in nanoscale FinFET with high-k gate dielectric. Based on the theory, we analyze the effects of geometrical dimensions and materials on the SCEs in nanoscale FinFET.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Analysis of SCEs in nanoscale FinFET with high-k gate dielectric\",\"authors\":\"Qian Xie, Jun Xu\",\"doi\":\"10.1109/SNW.2010.5562569\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We derive a three-dimensional (3-D) analytical model of scale length for nanoscale SOI tri-gate FET (SOI-FinFET) and discuss its significance. This work takes into account the difference in permittivity between the fin (channel) and the gate insulator, and thus permits this model accurate for the analysis of SCEs in nanoscale FinFET with high-k gate dielectric. Based on the theory, we analyze the effects of geometrical dimensions and materials on the SCEs in nanoscale FinFET.\",\"PeriodicalId\":6433,\"journal\":{\"name\":\"2010 Silicon Nanoelectronics Workshop\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 Silicon Nanoelectronics Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SNW.2010.5562569\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Silicon Nanoelectronics Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SNW.2010.5562569","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analysis of SCEs in nanoscale FinFET with high-k gate dielectric
We derive a three-dimensional (3-D) analytical model of scale length for nanoscale SOI tri-gate FET (SOI-FinFET) and discuss its significance. This work takes into account the difference in permittivity between the fin (channel) and the gate insulator, and thus permits this model accurate for the analysis of SCEs in nanoscale FinFET with high-k gate dielectric. Based on the theory, we analyze the effects of geometrical dimensions and materials on the SCEs in nanoscale FinFET.
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