集成MEMS技术的单模可调谐vcsel

B. Kogel, P. Debernardi, P. Westbergh, Å. Haglund, J. Gustavsson, J. Bengtsson, E. Haglund, A. Larsson
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引用次数: 1

摘要

图1a)给出了一种用于可调谐vcsel晶圆级集成的简单MEMS技术[1]。可调谐的VCSEL由一个“半VCSEL”和一个外镜组成,前者是一个没有顶部分布布拉格反射器(DBR)的VCSEL,后者是一个微机械薄膜(MEMS)。基于gaas的半vcsel包括底部DBR,具有5个量子阱(qw)的有源区域和用于电流限制的氧化物孔径。蚀刻的台面覆盖有抗反射涂层(AR-c),并嵌入低k介电介质(BCB)中。如图1 b)所示,光阻液液滴被用作牺牲层和预制体,用于制作弯曲微镜。在半vcsel上沉积介电DBR(7.5对TiO2/SiO2)和驱动层(50 nm Ni),然后蚀刻MEMS结构。最后,通过在丙酮中溶解牺牲层并在临界点干燥器中除去液体来释放镜像膜。通过向柔性MEMS上的驱动层注入加热电流来调谐VCSEL,该驱动层扩展并将腔谐振向更长的波长移动。在下面我们提出了一个优化的半对称腔设计单模发射。与[1]相比,平台直径被扩大(从120µm到200µm),以增加(即平坦)曲率半径(RoC)从420µm到1.2mm,同时将气隙保持在3.7µm左右。利用基于耦合模式理论[2]的三维模型,模拟了调谐过程中基模和高阶模的阈值增益(图1c))。不同氧化物孔径直径Dox的增益差异如图1所示。当Dox≤10µm时,腔体支持单基模,而在氧化物孔径处扩展的高阶横向模受到削波影响(当Dox≤5µm时,基模也受到影响)。图1 (e)显示了经过充分处理的可调谐VCSEL的显微镜图像。每个芯片包含一个8×8可调谐VCSEL阵列,占地面积为290µm×400µm。具有10µm氧化物孔径的可调谐VCSEL的光谱如图1f所示。在12 nm调谐范围内,VCSEL以基模发射,侧模抑制比SMSR≥25 dB。相比之下,传统的具有平顶DBR的850 nm不可调谐vcsel仅在Dox≤3µm时是单模的,并且通常在更高的电流密度下工作。
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Singlemode tunable VCSELs with integrated MEMS technology
A simple MEMS technology for wafer-scale integration of tunable VCSELs is presented in Fig. 1 a) [1]. The tunableVCSEL is composed of a “half-VCSEL”, which is a VCSEL without top distributed Bragg reflector (DBR), and an externalmirror, which is a micromachined membrane (“MEMS”). The GaAs-based half-VCSEL comprises a bottom DBR, an active region with 5 quantum wells (QWs), and an oxide aperture for current confinement. The etched mesa is capped with an antireflection coating (AR-c) and embedded in a low-k dielectric (BCB). Reflown photo-resist droplets are used as sacrificial layer and as preform for making curved micro-mirrors, as shown in Fig. 1 b). A dielectric DBR (7.5 pairs TiO2/SiO2) and an actuation layer (50 nm Ni) are deposited onto the half-VCSEL, and then the MEMS structure is etched. Finally, the mirror membrane is released by dissolving the sacrificial layer in acetone and removing the liquid in a critical point dryer. The VCSEL is tuned by injecting a heating current into the actuation layer on the flexible MEMS, which expands and shifts the cavity resonance towards longer wavelengths. In the followingwe present an optimized half-symmetric cavity design for singlemode emission. Compared to [1] the mesa diameter is enlarged (from 120µm to 200µm) to increase (i. e. flatten) the radius of curvature (RoC) from 420µm to 1.2mm, while keeping the air-gap at around 3.7µm. The threshold gain of fundamental mode and higher order mode during tuning are simulated (Fig. 1 c)) using a 3D model based on coupled mode theory [2]. The resulting gain difference for different oxide aperture diameters Dox is plotted in Fig. 1 d). The cavity supports the single fundamental mode for Dox ≤10µm, while themore expanded higher order transverse modes suffer from clipping at the oxide aperture (for Dox ≤5µm the fundamental mode is affected, too). A microscope image of a fully processed tunable VCSEL is shown in Fig. 1 e). Each chip contains an array of 8×8 tunable VCSELs with a small footprint of 290µm×400µm. The spectrum of a tunable VCSEL with 10µm oxide aperture is shown in Fig. 1 f). The VCSEL emits in fundamental mode with a sidemode suppression ratio SMSR≥25 dB over the tuning range of 12 nm. In comparison, conventional non-tunable 850-nm VCSELs with flat top DBR are singlemode only for Dox ≤3 µm and usually operated at higher current densities.
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