用于CMOS和CPL逻辑的Wallace树乘法器的设计与分析

应用数学与计算数学学报 Pub Date : 2018-03-28 DOI:10.1109/ICCPEIC.2018.8525224

S. Nagaraj, K. Thyagarajan, D. Srihari, K. Gopi

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引用次数: 2

摘要

本文设计并分析了用于CMOS和CPL逻辑器件的华莱士树乘法器。CPL逻辑是低功耗逻辑。本文的目的是比较CMOS和CPL逻辑的华莱士树乘法器的面积、功率和延迟。该设计采用HSPICE 180nm技术实现。Wallace Tree Multiplier是针对8位和16位设计的，使用3:2、4:2和5:2的压缩器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design and Analysis of Wallace Tree Multiplier for CMOS and CPL Logic

In this paper we have designed and analysed Wallace Tree Multiplier for CMOS and CPL Logics. CPL Logic is low power logic. This paper aims at comparing the area, power and delay of Wallace Tree Multiplier for CMOS and CPL Logics. The design is implemented using HSPICE for 180nm Technology. Wallace Tree Multiplier was designed for 8-bit and 16-bit using 3:2,4:2 and 5:2 compressors.

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应用数学与计算数学学报

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