F. Ouchet, D. Borrione, K. Morin-Allory, L. Pierre
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High-level symbolic simulation for automatic model extraction
This paper describes VSYML, a symbolic simulator that extracts formal models from VHDL descriptions. The generated models are adequate to formal reasoning in various frameworks. VSYML is a reimplementation of its ancestor Theosim; it brings various improvements e.g., with regard to arrays and other complex data types.
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