{"title":"介绍MULTIBUS II架构","authors":"William M Clemow","doi":"10.1016/0252-7308(85)90010-8","DOIUrl":null,"url":null,"abstract":"<div><p>The MULTIBUS II architecture is an open system bus architecture for general purpose 8-, 16- or 32-bit microcomputer systems design. The architecture incorporates multiple buses, allowing the designer to configure a system using the various buses to satisfy the cost and performance needs of his particular application. The parallel system bus iPSB contains a variety of advanced bus concepts that aim to enhance performance, reliability and ease of use. This article focuses on the advanced concepts of the iPSB bus.</p></div>","PeriodicalId":100687,"journal":{"name":"Interfaces in Computing","volume":"3 3","pages":"Pages 277-286"},"PeriodicalIF":0.0000,"publicationDate":"1985-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0252-7308(85)90010-8","citationCount":"1","resultStr":"{\"title\":\"Introduction to the MULTIBUS II architecture\",\"authors\":\"William M Clemow\",\"doi\":\"10.1016/0252-7308(85)90010-8\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>The MULTIBUS II architecture is an open system bus architecture for general purpose 8-, 16- or 32-bit microcomputer systems design. The architecture incorporates multiple buses, allowing the designer to configure a system using the various buses to satisfy the cost and performance needs of his particular application. The parallel system bus iPSB contains a variety of advanced bus concepts that aim to enhance performance, reliability and ease of use. This article focuses on the advanced concepts of the iPSB bus.</p></div>\",\"PeriodicalId\":100687,\"journal\":{\"name\":\"Interfaces in Computing\",\"volume\":\"3 3\",\"pages\":\"Pages 277-286\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1985-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://sci-hub-pdf.com/10.1016/0252-7308(85)90010-8\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Interfaces in Computing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/0252730885900108\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Interfaces in Computing","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/0252730885900108","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The MULTIBUS II architecture is an open system bus architecture for general purpose 8-, 16- or 32-bit microcomputer systems design. The architecture incorporates multiple buses, allowing the designer to configure a system using the various buses to satisfy the cost and performance needs of his particular application. The parallel system bus iPSB contains a variety of advanced bus concepts that aim to enhance performance, reliability and ease of use. This article focuses on the advanced concepts of the iPSB bus.
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