Session 2: Architectures for image processing

In the field of Signal Processing in general, and in particular in the Image Processing one, it is quite common to customize the underling architecture to improve computing efficiency. This section is dedicated to Architectures for Image Processing and four different papers will be presented. Solutions based on application specific processors, characterized on the processing requirements, may improve on board processing and facilitate data transmission from distributed computing nodes as presented in first paper. Memory hierarchy implementation and management is fundamental to improve computing efficiency. In this sense, the second paper investigates the usage of associative memories for pattern detection purposes and will apply them in the context of Clustered Neural Networks, while the third one presents a memory efficient architecture implementing in hardware the Multi-Scale Line Detector algorithm for real-time retinal blood vessel detection. Finally, the last paper is more system oriented, being focused on modelling techniques to derive and verify lossless compression IP cores.