An efficient minimum area spacing algorithm for noise reduction

With high clock frequencies, faster transistor rise/fall time, long signal wires, the use of wider wires and Cu material interconnects, the decreased spacing between adjacent wires, and the increased aspect ratio, the crosstalk noise is becoming an important design metric in digital circuits. For a risk-free layout solution of a chip, capacitive and inductive noises should be considered at various routing process stages. A formulation and efficient solution for the min-area spacing problem to satisfy maximum reliability in multiple coupled nets is provided. The noise model used can handle different wire widths, different spacing among wires, and different wire lengths. Experimental results show that the proposed framework redistributes the spacing among neighboring wires to achieve maximum reliability through the minimization of the maximum crosstalk noise in nets.