Contention-avoiding custom topology generation for network-on-chip

In this paper we present a methodology for custom topology generation, offering low latency and significantly reduced power consumption. The novelty of our approach lies in the objective - we focus on complete elimination of the contention on the links. It is achieved through alternate path generation, insertion of additional links and message scheduling. We also present a novel concept of Message Dependence Graph for traffic analysis. The methodology operates under application and design constraints, producing network topology along with routing paths. Experimental results confirming benefits of the proposed approach are provided.