On-orbit maintenance and reconfiguration of DSP based on FPGA

FPGA+DSP architecture is widely used in satellite digital processing systems. The satellite is in an environment where there is a lot of particle radiation and collisions. In order to avoid changes in stored code data brought by SEU (Single Event Upset), improve the system reliability, at the same time meet the current requirements of software on-orbit reconfiguration, the FPGA and DSP in the space-borne core processor need to have the ability of error correction and reconfiguration. To do this, FPGA and DSP programs need to be stored in external, writable memory. Nor Flash, with its high capacity and reliability, is often chosen as the memory for storing code. At present, the on-orbit maintenance of FPGA is usually realized by using Actel FPGA to conduct TMR (Triple Modular Redundancy), refresh and other processing on the FPGA code stored in Flash. Based on this idea, a T-shaped structure is constructed among FPGA, DSP and Flash for the architecture of the space-borne processor. As the master, FPGA controls Flash to complete TMR, error correction and on-orbit reconfiguration of DSP code. This method reduces hardware redundancy, gives consideration to autonomous maintenance and on-orbit reconfiguration, and increases system robustness. This method has been applied and fully verified in orbit.