An Approach for Multicast Routing in Networks-on-Chip

The main components for building today's computer systems are Chip Multiprocessors, where multiple processor cores are placed on the same chip. These cores can run several threads of an application or can run multiple applications at the same time. Efficient execution of such applications depends on the ability of the on-chip interconnect to support multicast with minimum overhead. Many of the existing works present efficient solutions to one-to-one and broadcast communication but for multicast they assume the existence of on-chip router capability to provide several point-to-point links one for each destination. In this paper we propose a new approach for multicast routing for on-chip networks with minimum hardware support. Our approach minimizes the average hop traversal of each replica within the network by selecting replication points based on the distribution density of the destination nodes. Experimental results have shown that link utilization and link power consumption have been reduced by 8.36% in case of an 8 x 8 mesh and for mesh networks of dimensions 12 x 12 and 16 x 16 the percentage reduction is 16%, showing the scalability of our approach.