FPGA synthesis of area efficient data path for reconfigurable FIR filter

Reconfigurable computing for DSP remains an active area of research as the need for integration with more traditional DSP technologies become apparent. Traditionally, most of the work in the field of reconfigurable computing was focused on fine-grained FPGA devices. Over the years, the focus was shifted from bit level granularity to a more coarse grained composition. In this paper, we present the synthesis of high-throughput and area efficient data path for reconfigurable Finite Impulse Response (FIR) filter. FIR filters have been and continue to be important building blocks in many DSP systems. It computes the output by multiplying a set of input samples with a set of coefficients followed by addition. Here, the multiplication and addition processess are based on the concept of Divide and Conquer approach. Separate multiplier and adder blocks are designed to model the FIR filter. The design was modeled using Verilog HDL and simulated and synthesized using Xilinx IS E 14.2. The design was also synthesized in Leonardo Spectrum. A comparison was made by implementing the design on different FPGA devices. The result shows that the proposed system has better device utilization in Virtex-5 FPGA.