Rodrigo Devigo, Liana Duenha, R. Azevedo, R. Santos
{"title":"MultiExplorer:用于多核系统芯片设计探索的工具集","authors":"Rodrigo Devigo, Liana Duenha, R. Azevedo, R. Santos","doi":"10.1109/ASAP.2015.7245727","DOIUrl":null,"url":null,"abstract":"This paper proposes MultiExplorer, a new toolset for MPSoCs modelling, experimentation, and design space exploration, by combining fast high-abstraction simulation and low-level physical estimates (power, area, and timing). The MultiExplorer infrastructure takes a range of high and low-level parameters to improve accuracy in the design of a multiprocessor system on a chip. Our toolset results show a viable alternative to explore multiprocessor scalability (1-64 cores) on affordable simulation times.","PeriodicalId":6642,"journal":{"name":"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","volume":"28 1","pages":"160-161"},"PeriodicalIF":0.0000,"publicationDate":"2015-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"MultiExplorer: A tool set for multicore system-on-chip design exploration\",\"authors\":\"Rodrigo Devigo, Liana Duenha, R. Azevedo, R. Santos\",\"doi\":\"10.1109/ASAP.2015.7245727\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes MultiExplorer, a new toolset for MPSoCs modelling, experimentation, and design space exploration, by combining fast high-abstraction simulation and low-level physical estimates (power, area, and timing). The MultiExplorer infrastructure takes a range of high and low-level parameters to improve accuracy in the design of a multiprocessor system on a chip. Our toolset results show a viable alternative to explore multiprocessor scalability (1-64 cores) on affordable simulation times.\",\"PeriodicalId\":6642,\"journal\":{\"name\":\"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)\",\"volume\":\"28 1\",\"pages\":\"160-161\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-07-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASAP.2015.7245727\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASAP.2015.7245727","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
MultiExplorer: A tool set for multicore system-on-chip design exploration
This paper proposes MultiExplorer, a new toolset for MPSoCs modelling, experimentation, and design space exploration, by combining fast high-abstraction simulation and low-level physical estimates (power, area, and timing). The MultiExplorer infrastructure takes a range of high and low-level parameters to improve accuracy in the design of a multiprocessor system on a chip. Our toolset results show a viable alternative to explore multiprocessor scalability (1-64 cores) on affordable simulation times.