A Fast And Memory-efficient Diagnostic Fault Simulation For Sequential Circuits

In this paper, a fast and memory-efficient diagnostic fault simulator for sequential circuits is proposed. In it, a two-level optimization technique is developed and used to prompt the processing speed. In the first high level, an efficient list, which stores the indistinguishable faults so far for each fault during simulation, and the list maintaining algorithm are applied, thus the number of diagnostic comparisons is minimized. In the second low level, a bit-parallel comparison is developed to speed up the comparing process. Therefore, the different diagnostic measure reports for a given test set can be generated very quickly. In addition, the simulator is extended to diagnose the single stuck-at device fault. Experimental results show that this diagnostic simulator achieves a significant speedup compared to previous methods.