Ferri Abolhassan, R. Drefenstedt, J. Keller, W. Paul, D. Scheerer
{"title":"论pram的物理设计","authors":"Ferri Abolhassan, R. Drefenstedt, J. Keller, W. Paul, D. Scheerer","doi":"10.1093/comjnl/36.8.756","DOIUrl":null,"url":null,"abstract":"We sketch the physical design of a prototype of a PRAM architecture based on Ranade’s Fluent Machine. We describe a specially developed processor chip with several instruction streams and a fast butterfly connection network. For the realization of the network we consider alternatively optoelectronic and electric transmission. We also discuss some basic software issues.","PeriodicalId":80982,"journal":{"name":"Computer/law journal","volume":"41 1","pages":"1-19"},"PeriodicalIF":0.0000,"publicationDate":"1992-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"90","resultStr":"{\"title\":\"On the Physical Design of PRAMs\",\"authors\":\"Ferri Abolhassan, R. Drefenstedt, J. Keller, W. Paul, D. Scheerer\",\"doi\":\"10.1093/comjnl/36.8.756\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We sketch the physical design of a prototype of a PRAM architecture based on Ranade’s Fluent Machine. We describe a specially developed processor chip with several instruction streams and a fast butterfly connection network. For the realization of the network we consider alternatively optoelectronic and electric transmission. We also discuss some basic software issues.\",\"PeriodicalId\":80982,\"journal\":{\"name\":\"Computer/law journal\",\"volume\":\"41 1\",\"pages\":\"1-19\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"90\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Computer/law journal\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1093/comjnl/36.8.756\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Computer/law journal","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1093/comjnl/36.8.756","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We sketch the physical design of a prototype of a PRAM architecture based on Ranade’s Fluent Machine. We describe a specially developed processor chip with several instruction streams and a fast butterfly connection network. For the realization of the network we consider alternatively optoelectronic and electric transmission. We also discuss some basic software issues.
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