High-Speed Comparator Design for RF-to-Digital Receivers

There is an increasing research interest in digitizing the radio frequency (RF) signal directly after the antenna to obtain a flexible wireless software-defined radio (SDR). This is mainly because the next generations, 4G and 5G standards, are allocated different bands for the same standard due to the worsening shortage of the available spectrum. In this paper a high-speed two-stage dynamic CMOS-latched comparator is designed using 65 nm CMOS process. It achieves sampling frequency up to 10 GHz with resolution of 10.11 bits and 13.28 bits at 1 GHz sampling clock while keeping the propagation delay less than 64 psec. for 1 mV input voltage difference. The proposed design targets SDRs based on pulse-width modulation (PWM) and RF sampling analog-to-digital converters (ADCs).