High throughput arbitrary sample rate converter for software radios

In modern digital communication systems, arbitrary sample rate conversion is the most computation intensive task. In addition, a reconfigurable sample rate converter is often required to meet the sampling rate requirements of different radio standards. This paper proposes a pipelined architecture for FPGA implementation of arbitrary rate converter employing cut-set retiming and Sum-Of-Power-Of-Two (SOPOT) techniques to achieve high throughput while reducing the hardware. The proposed architecture for 16 bit precision is designed and implemented using Xilinx ISE 14.2 and XC3S500E-4FG320 FPGA device. The implementation results show that the proposed architecture improves throughput by 4.5 times.