{"title":"下一个纳米电子时代合适的eDRAM配置综述","authors":"E. Amat, R. Canal, A. Calomarde, A. Rubio","doi":"10.5188/IJSMER.23.22","DOIUrl":null,"url":null,"abstract":"We summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform their memory cell counterparts, we explored different technological proposals and operational regimes where it can be located. The best memory cell performance is observed for the 3T1D-eDRAM cell when it is based on FinFET devices. Both device variability and SEU appear as key reliability issues for memory cells at sub-22nm technology node.","PeriodicalId":14339,"journal":{"name":"International journal of the Society of Materials Engineering for Resources","volume":"23 1","pages":"22-29"},"PeriodicalIF":0.0000,"publicationDate":"2018-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Review on suitable eDRAM configurations for next nano-metric electronics era\",\"authors\":\"E. Amat, R. Canal, A. Calomarde, A. Rubio\",\"doi\":\"10.5188/IJSMER.23.22\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform their memory cell counterparts, we explored different technological proposals and operational regimes where it can be located. The best memory cell performance is observed for the 3T1D-eDRAM cell when it is based on FinFET devices. Both device variability and SEU appear as key reliability issues for memory cells at sub-22nm technology node.\",\"PeriodicalId\":14339,\"journal\":{\"name\":\"International journal of the Society of Materials Engineering for Resources\",\"volume\":\"23 1\",\"pages\":\"22-29\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-03-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International journal of the Society of Materials Engineering for Resources\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.5188/IJSMER.23.22\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International journal of the Society of Materials Engineering for Resources","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.5188/IJSMER.23.22","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Review on suitable eDRAM configurations for next nano-metric electronics era
We summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform their memory cell counterparts, we explored different technological proposals and operational regimes where it can be located. The best memory cell performance is observed for the 3T1D-eDRAM cell when it is based on FinFET devices. Both device variability and SEU appear as key reliability issues for memory cells at sub-22nm technology node.
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