Structural test of programmed FPGA circuits

We present a new concept of the test method for FPGA devices. Instead of being focused on structural test of the device, the method tests logic and interconnection resources of the FPGA, that are actually used by implemented circuit. The method is based on reconfiguration ability of nowadays FPGAs and utilizes test vectors originally created for ASIC circuits. We present an idea of circuit partitioning and a transcription scheme, that converts the FPGA netlist to the ASIC one. Preliminary results of test patterns efficiency on transformed benchmark circuits are presented.