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引用次数: 99

摘要

我们研究了Windows NT性能的两个方面:在运行基准测试和商业应用程序的单处理器系统中内存访问的处理器带宽需求,以及在小型多处理器上商业数据库的锁定行为。我们的研究基于系统的完整动态执行跟踪,其中包括操作系统和应用程序在几秒钟内执行的所有指令(足够的时间来进行大量计算)。这些痕迹是在Alpha pc上获得的,使用一种名为PatchWrx的新软件工具,该工具利用Alpha架构的pal代码层来实现高效、全面的系统跟踪。因为Alpha版本的Windows NT使用与其他版本基本相同的代码库,因此执行几乎相同的调用序列、基本块和数据结构访问,我们相信我们的结论也适用于非Alpha版本的系统。本文描述了我们对PatchWrx的性能研究和有趣的方面。我们从研究中得出结论,处理器带宽可能是实现良好性能的一级瓶颈。在研究商业基准时,这一点尤为明显。操作系统代码和数据结构对内存访问负载的贡献不成比例。我们还发现,操作系统软件锁争用是阻止数据库基准测试在小型多处理器上扩展的一个因素,并且机器使用的缓存一致性协议引入了不必要的缓存干扰。
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Studies of Windows NT performance using dynamic execution traces
We studied two aspects of the performance of Windows NT: processor bandwidth requirements for memory accesses in a uniprocessor system running benchmark and commercial applications, and locking behavior of a commercial database on a small-scale multiprocessor. Our studies are based on full dynamic execution traces of the systems, which include all instructions executed by the operating system and applications over periods of a few seconds (enough time to allow for significant computation). The traces were obtained on Alpha PCs, using a new software tool called PatchWrx that takes advantage of the Alpha architecture’s PAL-code layer to implement efficient, comprehensive system tracing. Because the Alpha version of Windows NT uses substantially the same code base as other versions, and therefore executes nearly the same sequence of calls, basic blocks, and data structure accesses, we believe our conclusions are relevant for non-Alpha systems as well. This paper describes our performance studies and interesting aspects of PatchWrx. We conclude from our studies that processor bandwidth can be a first-order bottleneck to achieving good performance. This is particularly apparent when studying commercial benchmarks. Operating system code and data structures contribute disproportionately to the memory access load. We also found that operating system software lock contention was a factor preventing the database benchmark from scaling up on the small multiprocessor, and that the cache coherence protocol employed by the machine introduced more cache interference than necessary.
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