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引用次数: 2
摘要
本文将进一步提出一种改进的CMOS有源电阻线性化技术。最初提出的实现的主要优点是改进的线性度,小面积消耗和改进的频率响应。线性化有源电阻器I(V)特性的新方法将基于两个激励相反、偏置不同的准理想电路并联,其结果是将电路的线性度提高约一个数量级。由于这种原始的设计技术,电路线性度不受改变MOS晶体管工作的二阶效应的影响。使用FGMOS晶体管所获得的复杂性降低将有助于保持与经典技术的兼容性(经典的FGMOS器件可以被完全使用经典MOS器件的原始等效电路所取代)。由于所有MOS晶体管都工作在饱和区,因此电路的频率响应非常好。该电路采用0.35 μ m CMOS技术实现,SPICE仿真证实了理论估计结果,并显示在扩展输入范围(plusmn 500mV)和小电源电压值(plusmn 3V)下线性误差小于1%。
A new improved linearity active resistor using complementary functions
An original improved linearization technique for a CMOS active resistor will be further presented. The main advantages of the original proposed implementation are the improved linearity, the small area consumption and the improved frequency response. The new method for linearizing the I(V) characteristic of the active resistor will be based on a parallel connection of two quasi-ideal circuits opposite excited and different biased, having the result of improving the circuit linearity with about an order of magnitude. Because of this original design technique, the circuit linearity is not affected by the second-order effects that alter the MOS transistor operation. The reduced complexity obtained by using a FGMOS transistor will he made maintaining the compatibility with classical technologies (the classical FGMOS device could be replaced by an original equivalent circuit using exclusively classical MOS devices). The frequency response of the circuit is very good as a result of operating all MOS transistors in the saturation region. The circuit is implemented in 0.35 mum CMOS technology, the SPICE simulation confirming the theoretical estimated results and showing a linearity error under a percent for an extended input range (plusmn 500mV) and for a small value of the supply voltage (plusmn 3V)