Optimal FPGA memory allocation for image processing

In the field of computer vision, Field Programmable Gate Array (FGPA) limited de on-chip memory is difficult to meet the power, size and other requirements. To address this phenomenon, the study constructs a partitioning algorithm to achieve a balance between energy consumption and resource utilisation based on the analysis of memory resource allocation, overall power consumption and resource utilisation from the perspective of image processing technology. The power consumption of the balancing algorithm is lower compared to the optimised utilisation algorithm HLS tool, with both Block Ramdom Access Memory (BRAM) power consumption taking the value of 0.005; the dynamic power consumption takes the value range of 0.014–0.082. Compared to the High Level Synthesis (HLS) tool, the overall power consumption of the balancing algorithm and the optimised utilisation algorithm is significantly lower, with the values of 0.251 and 0.252 respectively, both with a reduction rate of approximately 30%. The accuracy rate of the proposed memory optimisation allocation algorithm is the highest among the four memory optimisation allocation algorithms and strategies on all three types of target scales. FPGA memory optimisation allocation strategy can guarantee to have lower power consumption while satisfying the same resource occupancy, and the model has in-depth application value in visual image vision technology.