All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance

In this paper, an all digital baseband data recovery algorithm using oversampling technique is presented. Our algorithm uses 5× clock to sample incoming data once around the middle. Sampling occurs exactly on the third clock after a data edge. If no data edge sensed, sampling occurs after five clocks from the previous sample. The system is designed to receive 50 Mbps data bit rate and uses a 250 MHz local clock to do the oversampling process. After injecting the clock with jitter at various magnitudes and frequencies, the design showed around 0.9 data Unit Interval (UIdata) jitter tolerance at frequencies higher than 25 MHz, in addition to a low Bit Error Rate (BER ≪ 10−11). The setup is implemented on an Altera Stratix II GX Field Programmable Gate Array (FPGA) while Agilent 81250 parallel Bit Error Ratio Tester (parBERT) is used to measure BER using Pseudo Random Bit Sequences (PRBS). Using 0.18 µm CMOS process, the design consumes as low power as 5 µW, which makes it effective for low power applications such as wireless image sensor nodes.