A New Core Level Utilization Algorithm for Energy-Efficient Multicore Systems

The energy consumption is becoming a constraint on all computer devices, from smartphones to supercomputers. Consequently, the focus has moved from performance to energy and power consumption. Design metrics are not only based solely on performance, as the energy performance of application executions is becoming the main aspect of architecture. Also, Design metrics depend on, the manufacturers of semiconductor chips which, have implemented multicore processors to boost the level of energy efficiency by using verified techniques for voltage and frequency scaling. To utilize the maximum potential of such architectures, we need to make the right decisions because parameters such as core type, frequency, and utilization typically affect power dissipation and performance. This paper proposes a new algorithm to achieve energy-efficient by monitoring core energy and level utilization control such as: Increasing the number of cores to execute the task, scaling voltage, and frequency. Based on the built model, we analyze the energy efficiency variations for different platform configurations providing the same level of performance. We show that trading the number and type of core with frequency and voltage level and core utilization rate can lead to substantial energy efficiency gains.