{"title":"0.18 /spl mu/m CMOS低功耗高速I/O接口","authors":"Yingyi Yan, T. Szymanski","doi":"10.1109/ICECS.2003.1301914","DOIUrl":null,"url":null,"abstract":"The design and implementation of a low power high speed differential signaling input/output (I/O) interface in 0.18 /spl mu/m CMOS technology is presented. The motivations for smaller signal swings in transmission are discussed. The prototype chip supports 4 Gbps data rate with less than 10 mA current at 1.8 V supply according to Cadence Spectre post-layout simulations. Performance comparisons between the proposed device and other signaling technologies reported recently are given.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"25 1","pages":"826-829 Vol.2"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Low power high speed I/O interfaces in 0.18 /spl mu/m CMOS\",\"authors\":\"Yingyi Yan, T. Szymanski\",\"doi\":\"10.1109/ICECS.2003.1301914\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design and implementation of a low power high speed differential signaling input/output (I/O) interface in 0.18 /spl mu/m CMOS technology is presented. The motivations for smaller signal swings in transmission are discussed. The prototype chip supports 4 Gbps data rate with less than 10 mA current at 1.8 V supply according to Cadence Spectre post-layout simulations. Performance comparisons between the proposed device and other signaling technologies reported recently are given.\",\"PeriodicalId\":36912,\"journal\":{\"name\":\"Czas Kultury\",\"volume\":\"25 1\",\"pages\":\"826-829 Vol.2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-12-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Czas Kultury\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2003.1301914\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"Arts and Humanities\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Czas Kultury","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2003.1301914","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Arts and Humanities","Score":null,"Total":0}
Low power high speed I/O interfaces in 0.18 /spl mu/m CMOS
The design and implementation of a low power high speed differential signaling input/output (I/O) interface in 0.18 /spl mu/m CMOS technology is presented. The motivations for smaller signal swings in transmission are discussed. The prototype chip supports 4 Gbps data rate with less than 10 mA current at 1.8 V supply according to Cadence Spectre post-layout simulations. Performance comparisons between the proposed device and other signaling technologies reported recently are given.
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