High Speed Approximate Carry Speculative Adder in Error Tolerance Applications

Approximate adders were proposed as feasible solution in error-tolerant applications to provide a proper trade-off with accuracy over other circuit-based metrics like energy, area, and delay. State of art of approximate adders are shown in this work to improve the operational features significantly. To acquire a most benefits of approximation, in this paper approximation at lower echelons is presented. Two speculative adders are proposed, one with approximate adder cell and other with Parallel prefix Adder cell. Gate level implementation of proposed model are designed and implemented. The cost functions are compared against various FPGA standard architectures. Results of proposed approach indicate an average of 46% improvement in Area Delay Product (ADP) and compared with existing approximate adders.