SIBA:用于图像处理的VLSI收缩阵列芯片

Q4 Computer Science 模式识别与人工智能 Pub Date : 1992-08-30 DOI:10.1109/ICPR.1992.202118

M. Patel, P. McCabe, N. Ranganathan

{"title":"SIBA:用于图像处理的VLSI收缩阵列芯片","authors":"M. Patel, P. McCabe, N. Ranganathan","doi":"10.1109/ICPR.1992.202118","DOIUrl":null,"url":null,"abstract":"Describes the design and implementation of a two-dimensional systolic array processor for applications in image processing and computer vision. The processor architecture is based on a SIMD array of 4-bit processing elements, interconnected by a mesh network with four nearest neighbors. The PE array is programmable allowing the user to develop application-specific algorithms for performing analysis on image data. A prototype VLSI chip has been designed implementing a single PE and has been submitted for fabrication. The chip is expected to operate at 25 MHz.<<ETX>>","PeriodicalId":34917,"journal":{"name":"模式识别与人工智能","volume":"5 1","pages":"15-18"},"PeriodicalIF":0.0000,"publicationDate":"1992-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"SIBA: a VLSI systolic array chip for image processing\",\"authors\":\"M. Patel, P. McCabe, N. Ranganathan\",\"doi\":\"10.1109/ICPR.1992.202118\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Describes the design and implementation of a two-dimensional systolic array processor for applications in image processing and computer vision. The processor architecture is based on a SIMD array of 4-bit processing elements, interconnected by a mesh network with four nearest neighbors. The PE array is programmable allowing the user to develop application-specific algorithms for performing analysis on image data. A prototype VLSI chip has been designed implementing a single PE and has been submitted for fabrication. The chip is expected to operate at 25 MHz.<<ETX>>\",\"PeriodicalId\":34917,\"journal\":{\"name\":\"模式识别与人工智能\",\"volume\":\"5 1\",\"pages\":\"15-18\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-08-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"模式识别与人工智能\",\"FirstCategoryId\":\"1093\",\"ListUrlMain\":\"https://doi.org/10.1109/ICPR.1992.202118\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"Computer Science\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"模式识别与人工智能","FirstCategoryId":"1093","ListUrlMain":"https://doi.org/10.1109/ICPR.1992.202118","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Computer Science","Score":null,"Total":0}

引用次数: 2

摘要

描述用于图像处理和计算机视觉应用的二维收缩阵列处理器的设计和实现。处理器架构基于4位处理元素的SIMD阵列，通过具有四个最近邻居的网状网络相互连接。PE阵列是可编程的，允许用户开发用于执行图像数据分析的特定应用算法。一个原型VLSI芯片已经设计实现一个单一的PE，并已提交制造。该芯片预计工作频率为25mhz。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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SIBA: a VLSI systolic array chip for image processing

Describes the design and implementation of a two-dimensional systolic array processor for applications in image processing and computer vision. The processor architecture is based on a SIMD array of 4-bit processing elements, interconnected by a mesh network with four nearest neighbors. The PE array is programmable allowing the user to develop application-specific algorithms for performing analysis on image data. A prototype VLSI chip has been designed implementing a single PE and has been submitted for fabrication. The chip is expected to operate at 25 MHz.<>

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