Hiroe Iwasaki, Takayuki Onishi, K. Nakamura, K. Nitta, T. Sano, Y. Nishida, K. Yokohari, Jia Su, N. Ono, R. Kusaba, Atsushi Sagata, M. Ikeda, A. Shimizu
{"title":"面向高质量4K/8K广播基础设施的专业H.265/HEVC编码器LSI","authors":"Hiroe Iwasaki, Takayuki Onishi, K. Nakamura, K. Nitta, T. Sano, Y. Nishida, K. Yokohari, Jia Su, N. Ono, R. Kusaba, Atsushi Sagata, M. Ikeda, A. Shimizu","doi":"10.1109/HOTCHIPS.2015.7477464","DOIUrl":null,"url":null,"abstract":"This article consists of a collection of slides from the authors' conference presentation. Some of the topics discussed include: Introduction and Background; NARA Architecture; NARA Key Features and Functions; NARA Chip Implementation; Target Applications; Conclusion.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"1 1","pages":"1-24"},"PeriodicalIF":0.0000,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure\",\"authors\":\"Hiroe Iwasaki, Takayuki Onishi, K. Nakamura, K. Nitta, T. Sano, Y. Nishida, K. Yokohari, Jia Su, N. Ono, R. Kusaba, Atsushi Sagata, M. Ikeda, A. Shimizu\",\"doi\":\"10.1109/HOTCHIPS.2015.7477464\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article consists of a collection of slides from the authors' conference presentation. Some of the topics discussed include: Introduction and Background; NARA Architecture; NARA Key Features and Functions; NARA Chip Implementation; Target Applications; Conclusion.\",\"PeriodicalId\":6666,\"journal\":{\"name\":\"2015 IEEE Hot Chips 27 Symposium (HCS)\",\"volume\":\"1 1\",\"pages\":\"1-24\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Hot Chips 27 Symposium (HCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HOTCHIPS.2015.7477464\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Hot Chips 27 Symposium (HCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTCHIPS.2015.7477464","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure
This article consists of a collection of slides from the authors' conference presentation. Some of the topics discussed include: Introduction and Background; NARA Architecture; NARA Key Features and Functions; NARA Chip Implementation; Target Applications; Conclusion.