ESSDERC 2007 - 37th European Solid State Device Research Conference

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1T-capacitorless bulk memory: Scalability and signal impact

Pub Date : 2007-09-11 DOI: 10.1109/ESSDERC.2007.4430945 G. Gouya, P. Malinge, B. Garni, F. Genevaux, R. Ferrant, S. Puget, V. Gravoulet, O. Bonnaud

Self-aligned μTrench phase-change memory cell architecture for 90nm technology and beyond

Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430918 A. Pirovano, F. Pellizzer, I. Tortorelli, R. Harrigan, M. Magistretti, P. Petruzza, E. Varesi, D. Erbetta, T. Marangon, F. Bedeschi, R. Fackenthal, G. Atwood, R. Bez

Gate-all-around Si-nanowire CMOS inverter logic fabricated using top-down approach

Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430938 K. Buddharaju, N. Singh, S. Rustagi, S. Teo, L. Wong, L. Tang, C. Tung, G. Lo, N. Balasubramanian, D. Kwong

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