Pub Date : 2007-09-11DOI: 10.1109/ESSDERC.2007.4430945
G. Gouya, P. Malinge, B. Garni, F. Genevaux, R. Ferrant, S. Puget, V. Gravoulet, O. Bonnaud
The 1-transistor floating body (1TFB) memory presents a possible solution for embedded memories, as it appears to scale, and does so with standard processing. This study investigates the signal limits of 1TFB memory as technology scales. It shows that although the signal DeltaVth remains nearly constant with scaling, the memory cells become susceptible to disturbance because the amount of stored charge decreases. In addition, the transistor mismatch increases with scaling, thus limiting the ability of conventional sensing methods to correctly read the memory.
{"title":"1T-capacitorless bulk memory: Scalability and signal impact","authors":"G. Gouya, P. Malinge, B. Garni, F. Genevaux, R. Ferrant, S. Puget, V. Gravoulet, O. Bonnaud","doi":"10.1109/ESSDERC.2007.4430945","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430945","url":null,"abstract":"The 1-transistor floating body (1TFB) memory presents a possible solution for embedded memories, as it appears to scale, and does so with standard processing. This study investigates the signal limits of 1TFB memory as technology scales. It shows that although the signal DeltaVth remains nearly constant with scaling, the memory cells become susceptible to disturbance because the amount of stored charge decreases. In addition, the transistor mismatch increases with scaling, thus limiting the ability of conventional sensing methods to correctly read the memory.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121087520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430918
A. Pirovano, F. Pellizzer, I. Tortorelli, R. Harrigan, M. Magistretti, P. Petruzza, E. Varesi, D. Erbetta, T. Marangon, F. Bedeschi, R. Fackenthal, G. Atwood, R. Bez
A novel self-aligned muTrench-based cell architecture for phase change memory (PCM) process is presented. The low-programming current and the good dimensional control of the sub-lithographic features achieved with the muTrench structure are combined with a self-aligned patterning strategy that simplify the integration process in term of alignment tolerances and of number of critical masks. The proposed architecture has been integrated in a 90 nm 128 Mb vehicle with programming currents of 300 muA and good distributions, demonstrating its suitability for the production of high-density PCM arrays at 90 nm and beyond.
{"title":"Self-aligned μTrench phase-change memory cell architecture for 90nm technology and beyond","authors":"A. Pirovano, F. Pellizzer, I. Tortorelli, R. Harrigan, M. Magistretti, P. Petruzza, E. Varesi, D. Erbetta, T. Marangon, F. Bedeschi, R. Fackenthal, G. Atwood, R. Bez","doi":"10.1109/ESSDERC.2007.4430918","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430918","url":null,"abstract":"A novel self-aligned muTrench-based cell architecture for phase change memory (PCM) process is presented. The low-programming current and the good dimensional control of the sub-lithographic features achieved with the muTrench structure are combined with a self-aligned patterning strategy that simplify the integration process in term of alignment tolerances and of number of critical masks. The proposed architecture has been integrated in a 90 nm 128 Mb vehicle with programming currents of 300 muA and good distributions, demonstrating its suitability for the production of high-density PCM arrays at 90 nm and beyond.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114645798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430938
K. Buddharaju, N. Singh, S. Rustagi, S. Teo, L. Wong, L. Tang, C. Tung, G. Lo, N. Balasubramanian, D. Kwong
We present, for the first time, the monolithic integration of Gate-Ail-Around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. The drive currents for N-and P-MOS transistors are matched using different number of channels for each to obtain symmetric pull-up and pull-down characteristics. Sharp ON-OFF transitions with high voltage gains (up to -45) are obtained which are best reported among the nanowire and carbon nanotube inverters. The inverters maintain their good transfer characteristics and noise margins for a wide range of VDD values, down to 0.2 V. Short circuit current at 0.2 V VDD is ~6 pA indicating excellent potential of these devices for low voltage and ultra low power applications. These results excel those reported in the literature for nanowire as well as FinFET (non-classical CMOS) inverters.
我们首次采用自顶向下的方法，将栅极环(GAA)硅纳米线场效应管集成到CMOS逻辑中。n - mos和P-MOS晶体管的驱动电流采用不同数量的通道进行匹配，以获得对称的上拉和下拉特性。在纳米线和碳纳米管逆变器中，获得了具有高电压增益(高达-45)的快速开关转换。逆变器在低至0.2 V的VDD值范围内保持良好的传输特性和噪声裕度。在0.2 V VDD时的短路电流为~6 pA，表明这些器件在低压和超低功耗应用中具有优异的潜力。这些结果优于文献中报道的纳米线和FinFET(非经典CMOS)逆变器。
{"title":"Gate-all-around Si-nanowire CMOS inverter logic fabricated using top-down approach","authors":"K. Buddharaju, N. Singh, S. Rustagi, S. Teo, L. Wong, L. Tang, C. Tung, G. Lo, N. Balasubramanian, D. Kwong","doi":"10.1109/ESSDERC.2007.4430938","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430938","url":null,"abstract":"We present, for the first time, the monolithic integration of Gate-Ail-Around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. The drive currents for N-and P-MOS transistors are matched using different number of channels for each to obtain symmetric pull-up and pull-down characteristics. Sharp ON-OFF transitions with high voltage gains (up to -45) are obtained which are best reported among the nanowire and carbon nanotube inverters. The inverters maintain their good transfer characteristics and noise margins for a wide range of VDD values, down to 0.2 V. Short circuit current at 0.2 V VDD is ~6 pA indicating excellent potential of these devices for low voltage and ultra low power applications. These results excel those reported in the literature for nanowire as well as FinFET (non-classical CMOS) inverters.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127134864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430930
Noel Rodriguez, Sorin Cristoloveanu, L. P. Nguyen, F. Gámiz
The carrier mobility in ultra-thin SOI transistors was measured at the front channel, back channel and in double gate mode (DG). A model for generalizing the mobility extraction method, based on the F-function, is proposed. In DG-mode the apparent mobility is the sum of front and back channel mobilities only if the two channels are independent (partially depleted or relatively thick fully depleted MOSFETs). In ultrathin transistors, the coupling effect should be accounted for achieving a balanced DG-mode. An outstanding apparent mobility enhancement in DG-mode is measured which cannot be explained by a 2-channels model. This result gives clear evidence of the benefit of volume inversion.
{"title":"Mobility issues in double-gate SOI MOSFETs: Characterization and analysis","authors":"Noel Rodriguez, Sorin Cristoloveanu, L. P. Nguyen, F. Gámiz","doi":"10.1109/ESSDERC.2007.4430930","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430930","url":null,"abstract":"The carrier mobility in ultra-thin SOI transistors was measured at the front channel, back channel and in double gate mode (DG). A model for generalizing the mobility extraction method, based on the F-function, is proposed. In DG-mode the apparent mobility is the sum of front and back channel mobilities only if the two channels are independent (partially depleted or relatively thick fully depleted MOSFETs). In ultrathin transistors, the coupling effect should be accounted for achieving a balanced DG-mode. An outstanding apparent mobility enhancement in DG-mode is measured which cannot be explained by a 2-channels model. This result gives clear evidence of the benefit of volume inversion.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126192045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430911
M. Agostinelli, M. Alioto, D. Esseni, L. Selmi
This paper investigates with a mixed device/circuit simulation methodology the effectiveness of DG SOI MOSFETs compared to conventional bulk MOSFETs for the implementation of low standby power circuit techniques. Our results indicate that DG MOSFETs offer significant advantages essentially because of the larger V T sensitivity to back-biasing.
本文采用混合器件/电路仿真方法研究了DG SOI mosfet与传统大块mosfet在实现低待机功率电路技术方面的有效性。我们的研究结果表明，DG mosfet具有显著的优势，主要是因为对反偏的较大V T灵敏度。
{"title":"Trading off static power and dynamic performance in CMOS digital circuits: bulk versus double gate SOI MOSFETs","authors":"M. Agostinelli, M. Alioto, D. Esseni, L. Selmi","doi":"10.1109/ESSDERC.2007.4430911","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430911","url":null,"abstract":"This paper investigates with a mixed device/circuit simulation methodology the effectiveness of DG SOI MOSFETs compared to conventional bulk MOSFETs for the implementation of low standby power circuit techniques. Our results indicate that DG MOSFETs offer significant advantages essentially because of the larger V T sensitivity to back-biasing.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122733597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430906
O. Bon, J. Roig, F. Morancho, S. Haendler, O. Gonnard, C. Raynaud
The static and dynamic analysis of the thermal resistance (RTH) in 65 nm SOI DriftMOS power devices is presented in this work. Experiment and numerical simulation are both used to compare DriftMOS devices integrated in 65 nm and 130 nm SOI technologies. Important RTHmiddot drop (between 40% and 60%) is found by experiment at 65 nm technology, basically due to the thinner buried oxide (BOX) layer. However, numerical simulation reveals a lower RTHmiddot reduction in the hottest point of the SOI active layer, shifted down about 15%. Furthermore, the RTHmiddot dependence with device geometrical parameters is investigated and the different layer contributions to the global thermal resistance are identified.
本文对65nm SOI DriftMOS功率器件的热阻(RTH)进行了静态和动态分析。通过实验和数值模拟，比较了采用65纳米和130纳米SOI技术集成的DriftMOS器件。在65纳米技术实验中发现重要的RTHmiddot下降(在40%到60%之间)，主要是由于较薄的埋藏氧化物(BOX)层。然而，数值模拟表明，SOI活动层的最热点的RTHmiddot下降幅度较小，下降了约15%。此外，研究了RTHmiddot与器件几何参数的关系，并确定了不同层对全局热阻的贡献。
{"title":"Thermal resistance reduction in power MOSFETs integrated in a 65nm SOI technology","authors":"O. Bon, J. Roig, F. Morancho, S. Haendler, O. Gonnard, C. Raynaud","doi":"10.1109/ESSDERC.2007.4430906","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430906","url":null,"abstract":"The static and dynamic analysis of the thermal resistance (RTH) in 65 nm SOI DriftMOS power devices is presented in this work. Experiment and numerical simulation are both used to compare DriftMOS devices integrated in 65 nm and 130 nm SOI technologies. Important RTHmiddot drop (between 40% and 60%) is found by experiment at 65 nm technology, basically due to the thinner buried oxide (BOX) layer. However, numerical simulation reveals a lower RTHmiddot reduction in the hottest point of the SOI active layer, shifted down about 15%. Furthermore, the RTHmiddot dependence with device geometrical parameters is investigated and the different layer contributions to the global thermal resistance are identified.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122543715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430961
S. Capraro, C. Bermond, T. Vo, J. Piquet, B. Fléchet, M. Thomas, A. Farcy, J. Torres, S. Crémer, E. Guichard, A. Haen
High frequency characterizations and simulations of 3D damascene metal-insulator-metal (MIM) capacitors are presented. We focused on the impact of the design on the performance of integrated capacitors. Results showed that properties of MIM capacitor get improved with specific design recommendations on electrodes shape.
{"title":"Design improvement of RF 3D MIM damascene capacitor","authors":"S. Capraro, C. Bermond, T. Vo, J. Piquet, B. Fléchet, M. Thomas, A. Farcy, J. Torres, S. Crémer, E. Guichard, A. Haen","doi":"10.1109/ESSDERC.2007.4430961","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430961","url":null,"abstract":"High frequency characterizations and simulations of 3D damascene metal-insulator-metal (MIM) capacitors are presented. We focused on the impact of the design on the performance of integrated capacitors. Results showed that properties of MIM capacitor get improved with specific design recommendations on electrodes shape.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129128496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430902
A. Castellazzi, M. Ciappa, W. Fichtner, E. Batista, J. Dienot, M. Mermet-Guyennet
This paper proposes the compact model development of a 6.5 kV field-stop IGBT module, for use in a circuit simulation environment. The model considers the realistic connection of IGBT-diode pairs: the description of semiconductor physics is coupled with self-heating effects; electro-magnetic phenomena associated with the package and layout are also taken into account. A selection of simulation examples demonstrates the validity of the proposed solution.
{"title":"Electro-thermal model of a high-voltage IGBT module for realistic simulation of power converters","authors":"A. Castellazzi, M. Ciappa, W. Fichtner, E. Batista, J. Dienot, M. Mermet-Guyennet","doi":"10.1109/ESSDERC.2007.4430902","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430902","url":null,"abstract":"This paper proposes the compact model development of a 6.5 kV field-stop IGBT module, for use in a circuit simulation environment. The model considers the realistic connection of IGBT-diode pairs: the description of semiconductor physics is coupled with self-heating effects; electro-magnetic phenomena associated with the package and layout are also taken into account. A selection of simulation examples demonstrates the validity of the proposed solution.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125669023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430923
Jing Zhu, J. Woo
In this paper, a novel concept of graphene channel FET with highly doped silicon source/drain is proposed. The current-voltage characteristics are analyzed and the optimized design parameters are presented by numerical analysis and device simulation. Such novel graphene channel MOSFETs on FDSOI or on insulator are found to have much superior current drive and transconductance than silicon MOSFETs.
{"title":"A novel graphene channel field effect transistor with Schottky tunneling source and drain","authors":"Jing Zhu, J. Woo","doi":"10.1109/ESSDERC.2007.4430923","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430923","url":null,"abstract":"In this paper, a novel concept of graphene channel FET with highly doped silicon source/drain is proposed. The current-voltage characteristics are analyzed and the optimized design parameters are presented by numerical analysis and device simulation. Such novel graphene channel MOSFETs on FDSOI or on insulator are found to have much superior current drive and transconductance than silicon MOSFETs.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130848576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430962
J. Manceau, A. Bajolet, S. Crémer, M. Quoirin, S. Bruyère, A. Sylvestre, P. Gonon
This paper describes a new measurement methodology based on LCR-meter tan(delta) measurement versus frequency. Directly integrated during parametric test, it gives information on capacitors key parameters like dielectric relaxation, potential dielectric contamination, extrinsic conduction, series resistance and process issue. The methodology is validated, thanks to the Kramers-Kronig relations, traditional I(V) measurements and series resistance model. Finally a practical example of a 3D MIM capacitor is studied.
{"title":"New capacitor parametric test methodology for process issues control","authors":"J. Manceau, A. Bajolet, S. Crémer, M. Quoirin, S. Bruyère, A. Sylvestre, P. Gonon","doi":"10.1109/ESSDERC.2007.4430962","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430962","url":null,"abstract":"This paper describes a new measurement methodology based on LCR-meter tan(delta) measurement versus frequency. Directly integrated during parametric test, it gives information on capacitors key parameters like dielectric relaxation, potential dielectric contamination, extrinsic conduction, series resistance and process issue. The methodology is validated, thanks to the Kramers-Kronig relations, traditional I(V) measurements and series resistance model. Finally a practical example of a 3D MIM capacitor is studied.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133660250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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