Complexity reduction of high-speed FIR filters using micro-genetic algorithm

Abstract

In the ASIC implementation, a long FIR filter can operate at high speed without pipelining if it is factorized into several short filters whose coefficients are in the form of the sum of signed powers-of-two terms. Such implementation reduces the hardware cost and lowers the power consumption significantly as it requires no multipliers. This paper presents a filter synthesis method that factorizes a long filter into several short filters and quantizes the coefficients of all short filters into signed powers-of-two values simultaneously using micro-genetic algorithm (/spl mu/GA). The proposed /spl mu/GA speeds up the optimization process greatly compared to conventional GA.