A Novel Dynamic Power Cutoff Technique (DPCT) for Active Leakage Reduction in Deep Submicron CMOS Circuits

Baozhen Yu, M. Bushnell
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引用次数: 18

Abstract

Due to the exponential increase in subthreshold leakage and gate leakage with technology scaling, leakage power is becoming a major fraction of total VLSI chip power in active mode. We present a novel active leakage power reduction technique, called the dynamic power cutoff technique (DPCT). First, the switching window for each gate, during which a gate makes its transitions, is identified by static timing analysis. Then, the circuit is optimally partitioned into different groups based on the minimal switching window (MSW) of each gate. Finally, power cutoff transistors are inserted into each group to control the power connections of that group. Each group is turned on only long enough for a wavefront of changing signals to propagate through that group. Since each gate is only turned on during a small timing window within each clock cycle, this significantly reduces active leakage power. This technique can also save standby leakage and dynamic power. Results on ISCAS'85 benchmark circuits modeled using 70 nm Berkeley predictive models (Cao et al., 2000) show up to 90% active leakage, 99% standby leakage, 54% dynamic power, and 72% total power savings
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一种新颖的动态功率截止技术(DPCT)用于深亚微米CMOS电路的有源泄漏降低
由于亚阈值泄漏和栅极泄漏随着技术的缩放呈指数级增长,在有源模式下,泄漏功率正在成为VLSI芯片总功率的主要部分。提出了一种新的有源泄漏功率降低技术,即动态功率切断技术(DPCT)。首先,通过静态时序分析确定每个门的切换窗口,在此期间一个门进行转换。然后,根据每个栅极的最小开关窗(MSW)将电路优化划分为不同的组。最后,在每一组中插入电源切断晶体管来控制该组的电源连接。每一组被打开的时间只够变化信号的波前在该组中传播。由于每个门只在每个时钟周期内的一个小定时窗口开启,这大大降低了有源泄漏功率。该技术还可以节省待机泄漏和动态功率。使用70 nm Berkeley预测模型(Cao et al., 2000)建模的ISCAS’85基准电路的结果显示,高达90%的有源泄漏,99%的待机泄漏,54%的动态功率和72%的总功耗节省
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