Improve the Dynamic Breakdown Voltage of SOI LDMOS Devices by Eliminating the Effect of Deep Depletion in Substrate

Abstract

In order to improve the transient breakdown voltage (TrBV) characteristics of silicon-on-insulator (SOI) laterally-diffused metal-oxide semiconductor (LDMOS), a new device structure is proposes in the paper. A P+ layer is introduced under the buried oxide (BOX) layer of the device to suppress the deep depletion (DD) effect in the substrate. The simulation results show that when the P+ layer concentration is greater than 4×1016 cm-3, TrBV characteristics of the new device is similar to static breakdown voltage (StBV) characteristics without reducing the withstand voltage. Therefore, the design of the dynamic withstand voltage of the device is greatly simplified. When the device temperature is equal to 500 K, its lowest operating frequency can be lower than 50 Hz. This can fully meet the conventional applications of SOI LDMOS devices.