Lei Shi, Jun Pang, Siliang Hua, Tiejun Zhang, C. Hou
{"title":"Implementation and analysis of configurable Real Time Address Trace Compressor for embedded microprocessors","authors":"Lei Shi, Jun Pang, Siliang Hua, Tiejun Zhang, C. Hou","doi":"10.1109/ISCIT.2007.4392005","DOIUrl":null,"url":null,"abstract":"Real-Time Address Trace Compression (RTATC) is a very useful method for debugging or analyzing software programs running on a processor-based system. Address trace compression means that the instruction addresses, which are produced in the instruction-fetch stage of the microprocessor, are compressed and out putted for later reconstruction and analysis. This paper presents a kind of RTATC method which includes three phases: branch filtering, address encoding and address compressing. A synthesizable RTL code for this method is constructed and integrated with a DSP&CPU processor to analyze the compressing effect and evaluate the hardware cost. The results show that our hardware is capable of real-time compression and achieving a very high compression ratio.","PeriodicalId":331439,"journal":{"name":"2007 International Symposium on Communications and Information Technologies","volume":"42 4","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Symposium on Communications and Information Technologies","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCIT.2007.4392005","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Real-Time Address Trace Compression (RTATC) is a very useful method for debugging or analyzing software programs running on a processor-based system. Address trace compression means that the instruction addresses, which are produced in the instruction-fetch stage of the microprocessor, are compressed and out putted for later reconstruction and analysis. This paper presents a kind of RTATC method which includes three phases: branch filtering, address encoding and address compressing. A synthesizable RTL code for this method is constructed and integrated with a DSP&CPU processor to analyze the compressing effect and evaluate the hardware cost. The results show that our hardware is capable of real-time compression and achieving a very high compression ratio.
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