{"title":"A Low-Complexity Decoder for Turbo Product Codes Based on Extended Hamming Codes","authors":"Yaqi Wang, Jun Lin, Zhongfeng Wang","doi":"10.1109/ICCT.2018.8599928","DOIUrl":null,"url":null,"abstract":"In this paper, a modified low-complexity Chase-II decoding algorithm for Turbo product codes(TPCs) and the corresponding hardware architecture are proposed. The proposed decoding algorithm is based on a low-complexity Fast Chase algorithm proposed in [1]. To further reduce the computational complexity, the number of the candidate codewords used to generate the extrinsic information is reduced to 2, and a new low-complexity method of calculating the extrinsic information is proposed. The proposed algorithm saves 44% real additions. The numerical simulation results show that the proposed algorithm has negligible performance loss if the component codes of TPCs are hamming codes. Moreover, an efficient hardware architecture for a $(128,120)^{2}$ extended Hamming turbo product code is also proposed. The proposed decoder is synthesised under the TSMC 90-nm CMOS technology. The synthesised results show that the proposed decoder reaches a 10.5 Gbps throughput with an area of 1.7 Mgates.","PeriodicalId":244952,"journal":{"name":"2018 IEEE 18th International Conference on Communication Technology (ICCT)","volume":"95 5","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 18th International Conference on Communication Technology (ICCT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCT.2018.8599928","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this paper, a modified low-complexity Chase-II decoding algorithm for Turbo product codes(TPCs) and the corresponding hardware architecture are proposed. The proposed decoding algorithm is based on a low-complexity Fast Chase algorithm proposed in [1]. To further reduce the computational complexity, the number of the candidate codewords used to generate the extrinsic information is reduced to 2, and a new low-complexity method of calculating the extrinsic information is proposed. The proposed algorithm saves 44% real additions. The numerical simulation results show that the proposed algorithm has negligible performance loss if the component codes of TPCs are hamming codes. Moreover, an efficient hardware architecture for a $(128,120)^{2}$ extended Hamming turbo product code is also proposed. The proposed decoder is synthesised under the TSMC 90-nm CMOS technology. The synthesised results show that the proposed decoder reaches a 10.5 Gbps throughput with an area of 1.7 Mgates.