Implementation and performance evaluation of three reconfigurable FFT cores for application in software defined radio system

Abstract

Fast Fourier Transform (FFT) is computationally an efficient algorithm that transforms a function in time domain to function in frequency domain. All 3G and 4G wireless technologies use OFDM and FFT is an integral block of transceiver loop. In this paper three FFT architectures are designed that fall within the Cooley-Tukey class of algorithms. These FFT designs are targeted for OFDM applications especially in future generations of Software Defined Radio (SDR) systems. The FFT is performed on 64-point complex valued input samples with 16-bit precision. Each core is optimized for a combination of area, power, and speed. The design is targeted for a partially reconfigurable FPGA platform such as Xilinx Virtex-4 or above. The FFT cores have been simulated in Model Sim and synthesized using Xilinx ISE software. The cores can be readily downloaded on to target FPGA board to check for run time configurability. The performance evaluation of these cores show that they run at clock frequency of about 80MHz.