Systolic array implementation of 2-D finite memory filters

Abstract

A scheme of systolic array implementation for recursive two-dimensional finite memory filters in real time is presented. A 2D state space model for recursive finite memory filters is used to derive a pipelined array for real-time implementation. The technique is based on block processing via iteration. The parallel implementation is a broadcast, calculate, and aggregate (BCA) paradigm with a regular communication structure. The processing elements (PEs) are simple and easy to design and verify, which makes the design cost effective.<>