Software-based on-chip thermal sensor calibration for DVFS-enabled many-core systems

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI:10.1109/DFT.2015.7315132

Sami Teravainen, M. Haghbayan, A. Rahmani, P. Liljeberg, H. Tenhunen

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引用次数: 6

Abstract

Due to increase in power density and temperature gradient in modern chips, multiple thermal sensors are deployed on the chip area to provide realtime temperature feedback for fine-grained dynamic thermal management (DTM) techniques. Thermal sensor accuracy is extremely prone to intra-die process variation and aging phenomena, and its report gradually drifts from the nominal value. This necessitates efficient calibration techniques to be applied before the sensor values are used. In addition, in modern many-core systems which are often enabled with dynamic voltage and frequency scaling (DVFS), thermal sensors located on cores are sensitive to the core's current voltage-frequency (VF) level, meaning that dedicated calibration is needed for each VF level. In this paper, we propose a general-purpose software-based auto-calibration strategy for thermal sensors without using any hardware infrastructures for DVFS-enabled many-core systems. We adopt a 2-point calibration method for calculating the calibration constants of each thermal sensor at each VF level. We demonstrate the efficiency of the proposed calibration strategy on a many-core platform, Intel's Single-chip Cloud Computer (SCC), covering all voltage and frequency combinations on the platform.

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基于软件的片上热传感器校准，支持dvfs的多核系统

由于现代芯片中功率密度和温度梯度的增加，在芯片区域上部署了多个热传感器，为细粒度动态热管理(DTM)技术提供实时温度反馈。热传感器精度极易出现模内工艺变化和老化现象，其报告值逐渐偏离标称值。这就需要在使用传感器值之前应用有效的校准技术。此外，在现代多核系统中，通常启用动态电压和频率缩放(DVFS)，位于核心上的热传感器对核心当前的电压频率(VF)水平很敏感，这意味着每个VF水平都需要专门的校准。在本文中，我们提出了一种通用的基于软件的热传感器自动校准策略，而不使用任何硬件基础设施用于支持dvfs的多核系统。我们采用两点定标法，计算每个VF电平下每个热传感器的定标常数。我们在多核平台，英特尔的单芯片云计算机(SCC)上证明了所提出的校准策略的效率，涵盖了平台上的所有电压和频率组合。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

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