Hardware implementation of quadtree based fractal image decoder

Abstract

This paper presents a simple hardware architecture for quadtree(QT) partitioning based fractal image decoder. The decoding process in fractal based compression technique is an iterative process and utilizes the parameters extracted during encoding for converging to a fixed point, that approximates the original image. The adaptive sized partitioning scheme provides details of various regions at different resolutions. In the proposed architecture, the mean-subtracted range and domain blocks are compared and matched at the encoder for fast convergence at the decoder. Though the convergence depends on the encoded information and the image itself, a maximum of four iterations are sufficient to reconstruct the image. The architecture has been implemented on Xilinx Virtex-5 FPGA operating at 164.4MHz. The proposed design spends less than 3 ms to decode a image of size 256 × 256 with average image quality exceeding 33dB.